1. Field of the Invention
The present invention relates to voltage regulator circuits. More particularly, the present invention relates to a circuit and method for reducing overshoots in adaptively biased voltage regulators.
2. Background Information
A conventional voltage regulator, which is sometimes referred to as a linear regulator, is used to provide power to low voltage digital and analog circuits, where point-of-load and line regulation is important. Conventional linear regulators suffer from poor transient response. Transient response is the behavior of the linear regulator after an abrupt change of either the load current (load response) or the input voltage (line response). A minimum undershoot and overshoot of the regulated voltage and a fast settling time is desired in the voltage regulator circuit.
FIG. 1 illustrates a conventional multi-loop voltage regulator circuit 100 that comprises a buffer (gain) amplifier 102 to push the gate pole of the output device 101 (e.g., a PMOS pass device) to high frequencies. Transistor 103 provides adaptive biasing of the buffer amplifier 102. Further shown in FIG. 1 are the equivalent series resistance (ESR) 111 and equivalent series inductance (ESL) 112 of the load capacitor 113. In the event of low loads, the out-pole formed by the load capacitor 113 and the load resistance 110 goes to low frequencies thereby also lowering the gate-pole. The voltage regulator circuit 100 uses the buffer (gain) amplifier 102 to adjust its gain in response to a load current passing through the output device 101 such that as the load current decreases, the gain increases. Conventional solutions to meet the fast settling time require the tail current of the buffer amplifier to be boosted at the start.
FIG. 2 illustrates a conventional voltage regulator circuit 200 using a buffer amplifier as an adaptive biased drive stage. The voltage regulator circuit 200 comprises a buffer amplifier 201 coupled to an output device 202 through a resistor 220. A feedback transistor device 203 is coupled between the non-inverting node of the buffer amplifier 201 and a far terminal of the resistor 220. The far terminal of the resistor 220 is coupled to a gate terminal of the device 202. An output terminal of the device 202 is coupled to a load circuit (ESR 211, ESL 212, capacitor 213 and resistor 210). The buffer amplifier 201 pushes the gate pole of the output device 202 to high frequencies. Transistor 203 provides adaptive biasing of the buffer amplifier 201. Although adaptive biasing improves the start up time of ultra low power voltage regulators, a disadvantage of the conventional solution 200 is that intolerable overshoots are observed at the regulator output that make the given circuit scheme unsuitable for its desired applications.
Referring to FIG. 3, a conventional voltage regulator circuit 300 comprising an excess bias tail current configuration is shown. The regulator 300 comprises an amplifier 301, which is coupled to an input signal at its non inverting (+) terminal. The amplifier 301 is coupled to an enable switch 302 and a current source (Itail—plus) 303. The current source 303 is terminated at a ground terminal. The load circuit of the voltage regulator circuit 300 comprises an R-L-C circuit (resistor 311, inductor 312 and a capacitor 313). A resistor load 310 is coupled at a common output node (Vout) of the amplifier 301. The enable switch 302 and the current source 303 switch in a pulsed current during start up of the voltage regulator circuit 300. When enabled, excess current Itail—plus is switched in to the tail of the amplifier 301, thereby improving the slew rate of the amplifier. Thus, the startup time of the voltage regulator circuit is reduced.
To limit overshoots in the conventional solutions (e.g., as illustrated in FIGS. 1, 2 and 3), either the adaptive biasing is slightly compromised or a pulsed tail current is switched in during start-up. Further disadvantages of conventional solutions include huge area demand for large currents, compensation at higher tail current during start up if not compensated at the load, and the need for a pulse generation for turning off the switched-in current after start-up if the regulator gets enabled with a signal (area impact). If the digital signal is not available during start-up, then design-complexity will increase (e.g., comparators may be used to sense the voltage and turn-off).
It is desirable to have an improved and reliable voltage regulator circuit that meets the circuit start up time specification, as well as maintain the output overshoots within desirable limits.